Samsung S5PC110 Manual page 964

S5PC110_UM
5.8.7.17 Device Endpoint 0 Transfer Size Register (DIEPTSIZ0, R/W, Address = 0xEC00_0910)
The application must modify this register before enabling endpoint 0. Once endpoint 0 is enabled using Endpoint
Enable bit of the Device Control Endpoint 0 Control registers (DIEPCTL0.EPEna/DOEPCTL0.EPEna), the core
modifies this register. The application can only read this register once the core has cleared the Endpoint Enable
bit.
Nonzero endpoints use the registers for endpoints 1-15.
When Scatter/Gather DMA mode is enabled, this register must not be programmed by the application. If the
application reads this register when Scatter/Gather DMA mode is enabled, the core returns all zeros.
DIEPTSIZ0 Bit
Reserved [31:21]
PktCnt [20:19]
Reserved [18:7]
XferSize [6:0]
-
Packet Count
Indicates the total number of USB packets that constitute the
Transfer Size amount of data for endpoint 0.
This field is decremented every time a packet is read from the
TxFIFO.
-
Transfer Size
Indicates the transfer size in bytes for endpoint 0. The core
interrupts the application only after it has exhausted the transfer
size amount of data. The transfer size can be set to the
maximum packet size of the endpoint, to be interrupted at the
end of each packet.
The core decrements this field every time a packet from the
external memory is written to the TxFIFO.
Description
5 USB2.0 HS OTG
R/W Initial State
- 11'h0
R/W 2'b0
- 12'h0
R/W 7'h0
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