Supports Clock Frequency Up To 200Mhz Block Diagram - Samsung S5PC110 Manual

S5PC110_UM 1 DRAM CONTROLLER

1.1.3 SUPPORTS CLOCK FREQUENCY UP TO 200MHZ BLOCK DIAGRAM

Figure 1-1 Overall Block Diagram
shows the overall block diagram of the controller. The block diagram shows the bus interface block,
Figure 1-1
scheduler block, and memory interface block, which connects and interfaces with the SEC LPDDR2 PHY.
The bus interface block saves the bus transactions for memory access that come from the AXI slave port to the
command queue. Additionally it saves the write data to the write buffer or sends the read data to the Master via
the AXI bus. It also acts as a read FIFO if AXI Master is not ready and has an APB interface for special function
registers/ direct commands and an AXI low power channel interface.
The Scheduler block uses the memory bank Finite State Machine (FSM) information to arbitrate the bus
transactions in the command queues and transforms the commands into a memory command type, which is sent
to the Memory interface block. It also controls the write and read data flow between the memory and the AXI
bus.
The Memory interface block updates each memory bank state according to the memory command coming from
the scheduler and sends the bank state back to the scheduler. It creates a memory command depending on the
memory latency and sends the command to the SEC LPDDR2 PHY via the PHY interface.
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