Samsung S5PC110 Manual page 527

S5PC110_UM
1.4.1.1 IRQ Status Register
(VICIRQSTATUS, R, Address=0xF200_0000, 0xF210_0000, 0xF220_0000, 0XF230_0000)
VICIRQSTATUS Bit
IRQStatus [31:0]
1.4.1.2 FIQ Status Register
(VICFIQSTATUS, R, Address=0xF200_0004, 0xF210_0004, 0xF220_0004, 0xF230_0004)
VICFIQSTATUS Bit
FIQStatus [31:0]
1.4.1.3 Raw Interrupt Status Register
(VICRAWINTR, R, Address=0xF200_0008, 0xF210_0008, 0xF220_0008, 0xF230_0008)
VICRAWINTR Bit
RawInterrupt [31:0]
1.4.1.4 Interrupt Select Register
(VICINTSELECT, R/W, Address=0xF200_000C, 0xF210_000C, 0xF220_000C, 0xF230_000C)
VICINTSELECT Bit
IntSelect [31:0]
Shows the status of the interrupts after masking by the
VICINTENABLE and VICINTSELECT Registers:
0 = Interrupt is inactive
1 = Interrupt is active.
There is one bit of the register for each interrupt source.
Shows the status of the FIQ interrupts after masking by the
VICINTENABLE and VICINTSELECT Registers:
0 = Interrupt is inactive
1 = Interrupt is active.
There is one bit of the register for each interrupt source.
Shows the status of the FIQ interrupts before masking by the
VICINTENABLE and VICINTSELECT Registers:
0 = Interrupt is inactive before masking
1 = Interrupt is active before masking
Because this register provides a direct view of the raw interrupt
inputs, the reset value is unknown.
There is one bit of the register for each interrupt source.
Selects interrupt type for interrupt request:
0 = IRQ interrupt
1 = FIQ interrupt
There is one bit of the register for each interrupt source.
1 VECTORED INTERRUPT CONTROLLER
Description
Description
Description
Description
Initial State
0x00000000
Initial State
0x00000000
Initial State
-
Initial State
0x00000000
1-20