Samsung S5PC110 Manual page 409

S5PC110_UM
4.10.4.10 Power Management Register (OSC_FREQ, R/W, Address = 0xE010_C100)
OSC_FREQ
Reserved
OSC_FREQ_VALUE
4.10.4.11 Power Management Register (OSC_STABLE, R/W, Address = 0xE010_C104)
OSC_STABLE
Reserved
OSC_CNT_VALUE
4.10.4.12 Power Management Register (PWR_STABLE, R/W, Address = 0xE010_C108)
PWR_STABLE
Reserved
PWR_CNT_VALUE
4.10.4.13 Power Management Register (MTC_STABLE, R/W, Address = 0xE010_C110)
MTC_STABLE
AUDIO
Reserved
CAM
TV
LCD
G3D
MFC
TOP
Bit
[31:4] Reserved
[3:0] Oscillator frequency scale counter
( OSC_FREQ_VALUE / oscillator_frequency > 200ns)
Bit
[31:20] Reserved
[19:0] 20-bit oscillator stable counter value.
It sets required period of time for oscillator to be stabilized.
Whenever oscillator is turned on, corresponding counter
increments from zero until it gets 16 times as big as this field
value.
The reference clock for the counter is external oscillator clock
input.
Bit
[31:20] Reserved
20-bit power stable counter value.
It sets required period of time for external power regulator to
be stabilized.
Whenever external power regulator is turned on,
[19:0]
corresponding counter increments from zero until it gets 16
times as big as this field value.
The reference clock for the counter is external oscillator clock
input.
Bit
[31:28] Memory power stabilization counter for Audio sub-block
[27:24] Reserved
[23:20] Memory power stabilization counter for CAM-block
[19:16] Memory power stabilization counter for TV-block
[15:12] Memory power stabilization counter for LCD-block
[11:8] Memory power stabilization counter for G3D block
[7:4] Memory power stabilization counter for MFC-block
[3:0] Memory power stabilization counter for TOP block
Description
Description
Description
Description
4 POWER MANAGEMENT
Initial State
0x000_0000
0xF
Initial State
0x000
0x0_FFFF
Initial State
0x000
0x0_FFFF
Initial State
0xF
0x0
0xF
0xF
0xF
0xF
0xF
0xF
4-49