Samsung S5PC110 Manual page 241

S5PC110_UM
2.2.55.82 GPIO Interrupt Control Registers (GPG2_INT_MASK, R/W, Address = 0xE020_093C)
GPG2_INT_MASK
Reserved
GPG2_INT_MASK[6]
GPG2_INT_MASK[5]
GPG2_INT_MASK[4]
GPG2_INT_MASK[3]
GPG2_INT_MASK[2]
GPG2_INT_MASK[1]
GPG2_INT_MASK[0]
2.2.55.83 GPIO Interrupt Control Registers (GPG3_INT_MASK, R/W, Address = 0xE020_0940)
GPG3_INT_MASK
Reserved
GPG3_INT_MASK[6]
GPG3_INT_MASK[5]
GPG3_INT_MASK[4]
GPG3_INT_MASK[3]
GPG3_INT_MASK[2]
GPG3_INT_MASK[1]
GPG3_INT_MASK[0]
Bit
[31:7] Reserved
[6] 0 = Enables Interrupt
1 = Masked
[5] 0 = Enables Interrupt
1 = Masked
[4] 0 = Enables Interrupt
1 = Masked
[3] 0 = Enables Interrupt
1 = Masked
[2] 0 = Enables Interrupt
1 = Masked
[1] 0 = Enables Interrupt
1 = Masked
[0] 0 = Enables Interrupt
1 = Masked
Bit
[31:7] Reserved
[6] 0 = Enables Interrupt
1 = Masked
[5] 0 = Enables Interrupt
1 = Masked
[4] 0 = Enables Interrupt
1 = Masked
[3] 0 = Enables Interrupt
1 = Masked
[2] 0 = Enables Interrupt
1 = Masked
[1] 0 = Enables Interrupt
1 = Masked
[0] 0 = Enables Interrupt
1 = Masked
2 GENERAL PURPOSE INPUT/ OUTPUT
Description
Description
Initial State
0
1
1
1
1
1
1
1
Initial State
0
1
1
1
1
1
1
1
2-206