Samsung S5PC110 Manual page 335

S5PC110_UM
3.7.4.8 Clock Divider Control Register (CLK_DIV7, R/W, Address = 0xE010_031C)
CLK_DIV7
Reserved
DPM_RATIO
Reserved
DVSEM_RATIO
Bit
[31:15] Reserved
[14:8] CLK_DPM clock divider ratio.
Source of DIVDPM clock divider is PCLK for IEM_IEC.
DPM_RATIO decides how often DPM channel increments for
IEM_IEC.
Refer to
Figure
[7] Reserved
[6:0] CLK_DVSEM clock divider ratio
Source of DIVDVSEM clock divider is PCLK for IEM_IEC.
DVSEM_RATIO decides how often PWM frame time slot is
advanced when IEM_IEC is in DVS emulation mode.
It should be guaranteed DIVDVSEM clock runs at 1MHz.
Refer to
Figure
Description
3-3.
3-3.
3 CLOCK CONTROLLER
Initial State
0x0
0x0
0
0x0
3-38