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S5PC110_UM
5.10 I/O DESCRIPTION
Signal
CSn0
CSn1
DA[2:0]
DD_RD[15:0]
DD_WR[15:0]
DD_wr_en
IORDY
INTRQ
DMARQ
DRESETn
DMACKn
DIORn
(HDMA_RDYn,
HSTROBE)
DIOWn
I/O
Description
O
Device chip selection signal
To select the control block registers
O
Device chip selection signal
To select the command block registers
O
register address signals
I
Read Data Bus
O
Write Data Bus
O
Data Output Enable Strobe
I
Data transfer wait signal.
DMA ready during UDMA write.
DMA strobe during UDMA read.
I
Device Interrupt signal.
I
The DMA request signal for data transfers
between host and device.
O
Device reset signal from host.
O
The DMA acknowledge signal that data
has been accepted or data is available.
O
IO Read Enable Strobe.
DMA ready during UDMA read.
Data strobe during UDMA write
O
IO Write Enable Strobe
Stop during UDMA read.
5 COMPACT FLASH CONTROLLER
Pad
XmsmCSn
XmsmWEn
XmsmADDR[2:0]
XmsmDATA[15:0]
XmsmDATA[15:0]
XmsmADDR[3]
XmsmADDR[4]
XmsmADDR[5]
XmsmADDR[6]
XmsmADDR[7]
XmsmRn
XmsmIRQn
Type
muxed
muxed
muxed
muxed
muxed
muxed
muxed
muxed
muxed
muxed
muxed
muxed
5-14
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