Samsung S5PC110 Manual page 729

S5PC110_UM
1.2.1.11 Configuration Register2 for DMA_MEM (CR2, R, Address = 0xFA20_0E08)
CR2
boot_addr
1.2.1.12 Configuration Register3 for DMA_MEM (CR3, R, Address = 0xFA20_0E0C)
CR3
INS
1.2.1.13 Configuration Register4 for DMA_MEM (CR4, R, Address = 0xFA20_0E10)
CR4
PNS
Bit
[31:0] Specifies the value of boot_addr[31:0] when DMAC exits from
reset.
32'b0
Bit
[31:0] Specifies the security state of interrupt outputs.
Bit [N] = 1: Assigns irq[N] to non-secure state.
32'hffff_ffff
Bit
[31:0] Specifies the security state of peripheral request interfaces.
Bit [N] = 1: Assigns peripheral request interface N to non-
secure state.
b11
Description
Description
Description
1 DMA CONTROLLER
Initial State
0
Initial State
0xFFFF_FFFF
Initial State
0x3
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