Samsung S5PC110 Manual page 30

2.2.35 Port Group MP1_3 Control Register........................................................................................... 2-111
2.2.36 Port Group MP1_4 Control Register........................................................................................... 2-112
2.2.37 Port Group MP1_5 Control Register........................................................................................... 2-112
2.2.38 Port Group MP1_6 Control Register........................................................................................... 2-113
2.2.39 Port Group MP1_7 Control Register........................................................................................... 2-113
2.2.40 Port Group MP1_8 Control Register........................................................................................... 2-114
2.2.41 Port Group MP2_0 Control Register........................................................................................... 2-114
2.2.42 Port Group MP2_1 Control Register........................................................................................... 2-115
2.2.43 Port Group MP2_2 Control Register........................................................................................... 2-115
2.2.44 Port Group MP2_3 Control Register........................................................................................... 2-116
2.2.45 Port Group MP2_4 Control Register........................................................................................... 2-116
2.2.46 Port Group MP2_5 Control Register........................................................................................... 2-117
2.2.47 Port Group MP2_6 Control Register........................................................................................... 2-117
2.2.48 Port Group MP2_7 Control Register........................................................................................... 2-118
2.2.49 Port Group MP2_8 Control Register........................................................................................... 2-118
2.2.50 Port Group ETC0 Control Register............................................................................................. 2-119
2.2.51 Port Group ETC1 Control Register............................................................................................. 2-120
2.2.52 Port Group ETC2 Control Register............................................................................................. 2-122
2.2.53 Port Group ETC3 is reserved ..................................................................................................... 2-124
2.2.54 Port Group ETC4 ........................................................................................................................ 2-124
2.2.55 GPIO Interrupt Control Registers ............................................................................................... 2-125
2.2.56 Port Group GPH0 Control Register ............................................................................................ 2-234
2.2.57 Port Group GPH1 Control Register ............................................................................................ 2-236
2.2.58 Port Group GPH2 Control Register ............................................................................................ 2-238
2.2.59 Port Group GPH3 Control Register ............................................................................................ 2-240
2.2.60 External Interrupt Control Registers ........................................................................................... 2-242
2.2.61 Extern Pin Configuration Registers in Power down Mode ......................................................... 2-262
3 Clock Controller .........................................................................................3-1
3.1 Clock Domains ......................................................................................................................................... 3-1
3.2 Clock Declaration ..................................................................................................................................... 3-2
3.2.1 Clocks from Clock Pads ................................................................................................................... 3-2
3.2.2 Clocks from CMU.............................................................................................................................. 3-3
3.3 Clock Relationship ................................................................................................................................... 3-4
3.3.1 Recommended PLL PMS Value for APLL........................................................................................ 3-5
3.3.2 Recommended PLL PMS Value for MPLL ....................................................................................... 3-6
3.3.3 Recommended PLL PMS Value for EPLL........................................................................................ 3-6
3.3.4 Recommended PLL PMS Value for VPLL........................................................................................ 3-7
3.4 Clock Generation ..................................................................................................................................... 3-8
3.5 Clock Configuration Procedure .............................................................................................................. 3-11
3.5.1 Clock Gating ................................................................................................................................... 3-11
3.6 Special Clock Description ...................................................................................................................... 3-12
3.6.1 Special Clock Table ........................................................................................................................ 3-12
3.7 Register Description............................................................................................................................... 3-14
3.7.1 Register Map .................................................................................................................................. 3-14
3.7.2 PLL Control Registers .................................................................................................................... 3-18
3.7.3 Clock Source Control Registers ..................................................................................................... 3-25
3.7.4 Clock Divider Control Register ....................................................................................................... 3-34
3.7.5 Clock Gating Control Register ........................................................................................................ 3-39
3.7.6 Clock Output Configuration Register .............................................................................................. 3-51
3.7.7 Clock Divider Status SFRs ............................................................................................................. 3-53
3.7.8 Clock MUX Status SFRs ................................................................................................................ 3-55