Samsung S5PC110 Manual page 588

S5PC110_UM
1.4.1.17 Counter Status Register for the Auto Refresh (ArefStatus, R, Address=0xF000_0050,
0xF140_0050)
AREFSTATUS
Reserved [31:16]
aref_cnt [15:0]
1.4.1.18 Memory Mode Registers Status Register (MrStatus, Read Only, Address = 0xF000_0054,
0xF140_0054)
MRSTATUS
Reserved [31:8]
mr_status
1.4.1.19 PHY Test Register 0 (PhyTest0, R/W, Address = 0xF000_0058, 0xF140_0058)
PHYTEST0
ctrl_fb_cnt4 [31:24]
Reserved [23:21]
ctrl_fb_oky [20:16]
Reserved [15:13]
ctrl_fb_err [12:8]
Reserved
ctrl_fb_start
Bit
Should be zero
Current Value of Auto Refresh Counter
Shows the current value of all bank auto refresh counter.
This is updated if a new t_refi is programmed into the
TimingAref register and decreases by 1 at the rising edge of
mclk.
An all bank auto refresh command is issued to memory device
and this counter is reloaded with TimingAref.t_ref if this
becomes zero.
Bit
Should be zero
[7:0] Mode Registers Status
Bit
Count Value for Control Channel
Should be zero
ctrl_fb_okay[4] : Error status for control,
ctrl_fb_okay[3:0] : Error status for data
Should be zero
ctrl_fb_err[4] : Error for control,
ctrl_fb_err[3:0] : Error for data
[7:5] Should be zero
[4:0] ctrl_fb_start[4] : Start for control,
ctrl_fb_start[3:0] : Start for data
Description
Description
Description
1 DRAM CONTROLLER
Initial
R/W
State
0x0
R 0xFFFF
Initial
R/W
State
0x0
R 0x0
Initial
R/W
State
R 0x0
0x0
R 0x0
0x0
R 0x0
0x0
R/W 0x0
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