Samsung S5PC110 Manual page 866

S5PC110_UM
3.4.2.12 FeedBack Clock Selection Register
•
FB_CLK_SEL_REG0, R/W, Address = 0xE130_002C
•
FB_CLK_SEL_REG1, R/W, Address = 0xE140_002C
FB_CLK_SELn
FB_CLK_SEL
3.4.2.13 PAD Driving Strength
PAD driving strength of SPI is controlled by setting drive strength control register in GPIO. SPI related SFR is
GPBDRV_SR (for SPI channel 0, 1).
Bit
[1:0] In master mode, SPI uses a clock which is feedback from the
SPICLK. The feedback clock is intended to capture safely the
slave TX signal which can be lagged if slave device is very far.
There are four kinds of feedback clocks which experience
different path delays. This register selects which one is to be
used.
Note that this register value is meaningless when SPI operates
in slave mode.
00 = SPICLK bypass (do not use feedback clock)
01 = A feedback clock with 90 degree phase lagging
10 = A feedback clock with 180 degree phase lagging
11 = A feedback clock with 270 degree phase lagging
NOTE: 90 degree phase lagging means 5ns delay in 50MHz
operating frequency.
3 SERIAL PERIPHERAL INTERFACE
Description Initial State
0x0
3-18