Samsung S5PC110 Manual page 903

S5PC110_UM
5.8.2.2 USB PHY Clock Control Register (UPHYCLK, R/W, Address = 0xEC10_0004)
UPHYCLK
Reserved [31:7] -
common_on_n1
Reserved
common_on_n0
Reserved
id_pullup0
clk_sel
Bit
[7] USBPHY1, Force XO, Bias, Bandgap, and PLL to Remain
Powered During a Suspend
This bit controls the power-down signals of sub-blocks in the
Common block if the USB PHY1 is suspended.
1'b0: 48MHz clock on clk48m_ohci is available at all times,
•
except in Suspend mode.
1'b1: 48MHz clock on clk48m_ohci is available at all times,
•
even in Suspend mode.
[6:5] -
[4] USBPHY0, Force XO, Bias, Bandgap, and PLL to Remain
Powered During a Suspend
This bit controls the power-down signals of sub-blocks in the
Common block if the USB PHY0 is suspended.
1'b0: 48MHz clock on clk48m_ohci is available at all times,
•
except in Suspend mode.
1'b1: 48MHz clock on clk48m_ohci is available at all times,
•
even in Suspend mode.
[3] -
[2] USBPHY0, Analog ID Input Sample Enable
1'b0: id_dig disable.
•
1'b1: id_dig enable. (The id_dig output is valid, and within
•
20ms, id_dig must indicate the type of plug connected.)
[1:0] USBPHY0 &1 Reference Clock Frequency Select for PLL
2'b00: 48MHz
•
2'b01: Reserved
•
2'b10: 12MHz
•
2'b11: 24MHz
•
Description
5 USB2.0 HS OTG
R/W Initial State
- 25'h0
R/W 1'b0
-
R/W 1'b0
- 1'b0
R/W 1'b0
R/W 2'b00
5-27