Samsung S5PC110 Manual page 847

S5PC110_UM
2.5.1.3 Multi-Master I
•
I2CADD0, R/W, Address = 0xE180_0008
•
I2CADD2, R/W, Address = 0xE1A0_0008
•
I2CADD_HDMI_DDC, R/W, Address = 0xFAB0_0008
•
I2CADD_HDMI_PHY, R/W, Address = 0xFA90_0008
I2CADD Bit
Slave address [7:0]
2.5.1.4 Multi-Master I
•
I2CDS0, R/W, Address = 0xE180_000C
•
I2CDS2, R/W, Address = 0xE1A0_000C
•
I2CDS_HDMI_DDC, R/W, Address = 0xFAB0_000C
•
I2CDS_HDMI_PHY, R/W, Address = 0xFA90_000C
I2CDS Bit
Data shift [7:0]
2
C-Bus Address Register
7-bit slave address, latched from the I
If serial output enable = 0 in the I2CSTAT, I2CADD is write-
enabled. The I2CADD value is read any time, regardless of the
current serial output enable bit (I2CSTAT) setting.
Slave address: [7:1]
Not mapped : [0]
2
C-Bus Transmit/Receive Data Shift Register
8-bit data shift register for I
If serial output enable = 1 in the I2CSTAT, I2CDS is write-enabled.
The I2CDS value is read any time, regardless of the current serial
output enable bit (I2CSTAT) setting.
Description
2
C-bus.
Description
2
C-bus Tx/Rx operation.
2 IIC-BUS INTERFACE
Initial State
Undefined
Initial State
Undefined
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