Samsung S5PC110 Manual page 985

S5PC110_UM 7 SD/MMC CONTROLLER
7.4.3 SD CLOCK STOP SEQUENCE
Figure 7-4 SD Clock Stop Sequence
The flow chart to stop the SD Clock is shown in The Host Driver does not stop the SD Clock if a SD
Figure 7-4
transaction takes place on the SD Bus -- namely, either Command Inhibit (DAT) or Command Inhibit (CMD) in the
Present State register is set to 1.
1. Set SD Clock Enable (ENSDCLK) in the Clock Control register to 0. After ENSDCLK is set, the Host
Controller stops SD Clock.
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