Special Function Register - Samsung S5PC110 Manual

S5PC110_UM

3.4.2 SPECIAL FUNCTION REGISTER

3.4.2.1 SPI Configuration Register
•
CH_CFG0, R/W, Address = 0xE130_0000
•
CH_CFG1, R/W, Address = 0xE140_0000
CH_CFGn
HIGH_SPEED_EN
SW_RST
SLAVE
CPOL
CPHA
RX_CH_ON
TX_CH_ON
NOTE: SPI controller should reset when
1. Reconfiguration SPI registers.
2. Error interrupt occurred.
Bit
[6] Slave TX output time control bit.
If this bit is enabled, slave TX output time is reduced as much as
half period of SPICLKout period.
NOTE: This bit is valid only in CPHA 0.
0 = Disables
1 = Enables
[5] Software reset.
The following registers and bits are cleared by this bit.
Rx/Tx FIFO Data, SPI_STATUS Once reset, this bit must be clear
manually.
0 = Inactive
1 = Active
[4] Whether SPI Channel is Master or Slave
0 = Master
1 = Slave
[3] Determines whether active high or active low clock
0 = Active High
1 = Active Low
[2] Select one of the two fundamentally different transfer format
0 = Format A
1 = Format B
[1] SPI Rx Channel On
0 = Channel Off
1 = Channel On
[0] SPI Tx Channel On
0 = Channel Off
1 = Channel On
3 SERIAL PERIPHERAL INTERFACE
Description Initial State
0
0
0
0
0
0
0
3-9