Dma Control Registers - Samsung S5PC110 Manual

S5PC110_UM

3.8.3 DMA CONTROL REGISTERS

3.8.3.1 DMA Source Address Register (DMA_SRC_ADDR, R/W, Address = 0xB060_0400)
DMA_SRC_ADDR
SA
3.8.3.2 DMA Source Configuration Register (DMA_SRC_CFG, R/W, Address = 0xB060_0404)
DMA_SRC_CFG
-
SBL
-
SAM
-
SDW
Bit
[31:0]
Source Address
Source address on the AHB for the DMA operation.
The start address for the DMA engine to perform read
operation.
Bit
[31:19] Reserved
[18:16]
Source Burst Length
Burst length during the source memory access on the AHB for
the DMA operation.
This burst length is valid only when the memory address is
aligned. The DMA engine requires that the memory address
should be the multiple of the HSIZE (data width) x HBURST
(burst length) to initiate the burst transfer on the AHB during
the DMA transfer. If this address alignment condition is not
satisfied, the actual burst length on the AHB will be single until
this condition is met.
000b = Single
001b = Reserved
010b = 4-Burst
011b = 8-Burst
100b = 16-Burst
101b = Reserved
110b = Reserved
111b = Reserved
[15:9] Reserved
[8]
Source Addressing Mode
This bit refers to addressing mode during the source memory
access on the AHB for the DMA operation.
The incremental addressing mode is used for the general DMA
operation and the constant mode is used to access repeatedly
the specific address like a data register.
0b = Incremental addressing mode
1b = Constant addressing mode
[7:2] Reserved
[1:0]
Source Data Width
Access size during the source memory access on the AHB for
the DMA operation.
The data width is valid only if the memory address is aligned.
To initiate the AHB transfer, the DMA engine requires that the
Description
Description
3 ONENAND CONTROLLER
Initial State
00000000h
Initial State
-
100b
-
0b
-
10b
3-30