Iec Related Registers - Samsung S5PC110 Manual

S5PC110_UM

5.5.2 IEC RELATED REGISTERS

5.5.2.1 DPC Control Register (IECDPCCR, R/W, Address = 0xE080_0000)
IECDPCCR Bit
Reserved [31:8]
Max [7:5]
Performance
mapping index
value
Synchronous [4]
Mode
Handshaking
Enable
IEC Software [3]
Debug
Emulation
IEC Max Perf [2]
Enable
IEC PWM DVS [1]
En
IEC Enable [0]
Reserved, read undefined, do not modify.
When IECMAXPERF goes high, the IEC requests maximum
performance level which is decided by this register value.
The reset value is 3'b111 which is literally max performance.
However, if 3'b111 performance level needs overdrive, it is not
desirable to overdrive SoC on every interrupt (MAXPERF case). In
that case, software programs this register as lower value than the
value needs overdrive.
Enable/disable the use of the synchronous mode handshaking
control signals.
0 = Synchronous mode handshaking disabled, also the reset value
1 = Synchronous mode handshaking enabled.
When this bit is set, the synchronous mode handshaking signals
are used to control entry and exit from the maximum performance
mode.
When this bit is cleared, the handshaking signals are not used.
Control to debug performance scaling.
0 = IEC performance scaling software debug disabled, also the
reset value
1 = IEC performance scaling software debug enabled.
When this bit is seta, the performance level driven out of the
IECTGTDVCIDX is set to maximum regardless of the software
request. The performance level changes are only visible on
IECTGTDCGIDX.
Enable/disable maximum performance mode override.
0 = IEC maximum performance mode disabled, also the reset value
1 = IEC maximum performance mode enabled.
When this bit is set, the maximum performance mode is enabled
and therefore whenever IECMAXPERF goes high, the IEC
requests maximum performance level regardless of the current
software request.
Enable/disable the IEC PWM DVS mode.
0 = IEC PWM DVS mode disabled, also the reset value
1 = IEC PWM DVS mode enabled.
When this bit is set, the IEC requests power through the
IECPWRREQ output. The target performance index outputs are set
to either maximum or minimum depending on the PWM state.
Controls enabling and disabling of the IEC.
0 = IEC Disabled, also the reset value
1 = IEC Enabled
When this bit is set, the IEC is enabled for performance scaling.
When the bit is cleared, the IEC always requests maximum
performance.
5 INTELLIGENT ENERGY MANAGEMENT
Description Initial State
0
0x7
0
0
0
0
0
5-22