Samsung S5PC110 Manual page 629

S5PC110_UM
3.8.2.3 OneNAND Interface Async Timing Control Register
(ONENAND_IF_ASYNC_TIMING_CTRL, R/W, Address = 0xB060_0108)
ONENAND_IF_
ASYNC_TIMING
_CTRL
- [31:16]
WHL [15:12]
WLL
OHL
OLL
Bit
Reserved
nWE High Length
nWE signal is held to high for WHL clock time at OneNAND
asynchronous read/ write execution.
0000b = Reserved (Do NOT Use)
0001b = 1 CLK
0010b = 2 CLK
... ...
1111b = 15 CLK
[11:8]
nWE Low Length
nWE signal is held to low for WLL clock time at OneNAND
asynchronous read/ write execution.
0000b = Reserved (Do NOT Use)
0001b = 1 CLK
0010b = 2 CLK
... ...
1111b = 15 CLK
[7:4]
nOE High Length
nOE signal is held to high for OHL clock time at OneNAND
asynchronous read/ write execution.
0000b = Reserved (Do NOT Use)
0001b = 1 CLK
0010b = 2 CLK
... ...
1111b = 15 CLK
[3:0]
nOE Low Length
nOE signal is held to low for (OLL+2) clock time at OneNAND
asynchronous read/ write execution.
0000b = 2 CLK
0001b = 3 CLK
0010b = 4 CLK
... ...
1110b = 16 CLK
1111b : Reserved (Do NOT Use)
Description
3 ONENAND CONTROLLER
Initial State
-
3h
4h
1h
5h
3-27