Stop Mode - Samsung S5PC110 Manual

S5PC110_UM

4.3.5 STOP MODE

In STOP mode, clock to modules (except RTC module), PLLs, and unnecessary oscillators are selectively
disabled to minimize dynamic power consumption. In this mode, Cortex-A8 Core enters into Standby mode.
Therefore, current application program that is running in NORMAL mode stops in STOP mode and waits for
wakeup event to resume.
To enter the STOP mode,
1. Make sure all PLLs are running before entering low-power mode.
This can be done by checking APLL_CON0, MPLL_CON, EPLL_CON0, VPLL_CON register.
2. Cut power off for all sub-blocks (LCD, CAM, TV, 3D, MFC) and verifies it is finised.
3. Set ARM_LOGIC field of STOP_CFG register to 2'b10. Set TOP_LOGIC field of STOP_CFG register to 2'b10.
4. Set other fields of STOP_CFG based on the users' requirements.
5. Set CFG_STANDBYWFI field of PWR_CFG to 2'b10.
6. Set SYSCON_INT_DISABLE field of OTHERS to 1'b1
7. Execute Wait-For-Interrupt instruction (WFI). If SYSCON_INT_DISABLE field of OTHERS is still 1'b1 after
calling wfi instruction, this indicates wfi instruction is ignored by the processor and
user should call wfi instruction again.
The SYSCON performs the following sequence to enter STOP mode.
1. Complete all active bus transactions.
2. Complete all active memory controller transactions.
3. Allow external DRAM to enter self-refresh mode (to preserve DRAM contents).
4. Mask clock input using internal signal in SYSCON.
5. Disable all PLLs.
6. Selectively disable OSCs except 32.768KHz.
In the above procedure, to finish all active bus transactions, SYSCON asserts CSYSREQs for AXI interface
components (AXI masters). If SYSCON confirms that all CSYSACKs and CACTIVEs from all AXI masters become
low, then it will check that CSYSACK and CACTIVE from external memory controller become low after it asserts
CSYSREQ to external memory controller to low. Then it confirms that CSYSACK and CACTIVE from external
memory controller become low and proceeds to next step.
4 POWER MANAGEMENT
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