Samsung S5PC110 Manual page 919

S5PC110_UM
5.8.3.7 Core Interrupt Mask Register (GINTMSK, R/W, Address = 0xEC00_0018)
This register works with the Core Interrupt register to interrupt the application. If an interrupt bit is masked, the
interrupt associated with that bit will not be generated. However, the Core Interrupt (GINTSTS) register bit
corresponding to that interrupt will still be set.
•
Mask interrupt: 1'b0
•
Unmask interrupt: 1'b1
GINTMSK
WkUpIntMsk
SessReqIntMsk
DisconnIntMsk
ConIDStsChngMsk
LPM_IntMsk
PTxFEmpMsk
HChIntMsk
PrtIntMsk
ResetDetMsk
FetSuspMsk
incomplPMsk
incompISOOUTMsk
incompISOINMsk
OEPIntMsk
INEPIntMsk
Reserved
Reserved
EOPFMsk
ISOOutDropMsk
EnumDoneMsk
USBRstMsk
USBSuspMsk
ErlySuspMsk
Reserved
Reserved
GOUTNakEffMsk
GINNakEffMsk
NPTxFEmpMsk
RxFLvlMsk
SofMsk
Bit
[31] Resume/ Remote Wakeup Detected Interrupt Mask
[30] Session Request/ New Session Detected Interrupt Mask
[29] Disconnect Detected Interrupt Mask
[28] Connector ID Status Change Mask
[27] LPM Transaction Received Interrupt Mask
[26] Periodic TxFIFO Empty Mask
[25] Host Channels Interrupt Mask
[24] Host Port Interrupt Mask
[23] Reset Detected Interrupt Mask
[22] Data Fetch Suspended Mask
[21] Incomplete Periodic Transfer Mask
Incomplete Isochronous OUT Transfer Mask
[20] Incomplete Isochronous IN Transfer Mask
[19] OUT Endpoints Interrupt Mask
[18] IN Endpoints Interrupt Mask
[17] -
[16] -
[15] End of Periodic Frame Interrupt Mask
[14] Isochronous OUT Packet Dropped Interrupt Mask
[13] Enumeration Done Mask
[12] USB Reset Mask
[11] USB Suspend Mask
[10] Early Suspend Mask
[9] -
[8] -
[7] Global OUT NAK Effective Mask
[6] Global Non-Periodic IN NAK Effective Mask
[5] Non-Periodic TxFIFO Empty Mask
[4] Receive FIFO Non-Empty Mask
[3] Start of (micro)Frame Mask
Description
5 USB2.0 HS OTG
R/W Initial State
R/W 1'b0
R/W 1'b0
R/W 1'b0
R/W 1'b0
R/W 1'b0
R/W 1'b0
R/W 1'b0
R/W 1'b0
R/W 1'b0
R/W 1'b0
R/W 1'b0
-
R/W 1'b0
R/W 1'b0
R/W 1'b0
- 1'b0
- 1'b0
R/W 1'b0
R/W 1'b0
R/W 1'b0
R/W 1'b0
R/W 1'b0
R/W 1'b0
- 1'b0
- 1'b0
R/W 1'b0
R/W 1'b0
R/W 1'b0
R/W 1'b0
R/W 1'b0
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