Samsung S5PC110 Manual page 332

S5PC110_UM
3.7.4.2 Clock Divider Control Register (CLK_DIV1, R/W, Address = 0xE010_0304)
CLK_DIV1
CSIS_RATIO
Reserved
FIMD_RATIO
CAM1_RATIO
CAM0_RATIO
Reserved
TBLK_RATIO
3.7.4.3 Clock Divider Control Register (CLK_DIV2, R/W, Address = 0xE010_0308)
CLK_DIV2
Reserved
G2D_RATIO
MFC_RATIO
G3D_RATIO
Bit
[31:28] DIVCSIS clock divider ratio,
SCLK_CSIS = MOUTCSIS / (CSIS_RATIO + 1)
[27:24] Reserved
[23:20] DIVFIMD clock divider ratio,
SCLK_FIMD = MOUTFIMD / (FIMD_RATIO + 1)
[19:16] DIVCAM1 clock divider ratio,
SCLK_CAM1 = MOUTCAM1 / (CAM1_RATIO + 1)
[15:12] DIVCAM0 clock divider ratio,
SCLK_CAM0 = MOUTCAM0 / (CAM0_RATIO + 1)
[11:4] Reserved
[3:0] DIVTBLK clock divider ratio,
SCLK_PIXEL= SCLKVPLL/ (TBLK_RATIO + 1)
Bit
[31:12] Reserved
[11:8] DIVG2D clock divider ratio,
SCLKG2D= MOUTG2D / (G2D_RATIO + 1)
[7:4] DIVMFC clock divider ratio,
SCLKMFC= MOUTMFC / (MFC_RATIO + 1)
[3:0] DIVG3D clock divider ratio,
SCLKG3D= MOUTG3D / (G3D_RATIO + 1)
Description
Description
3 CLOCK CONTROLLER
Initial State
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Initial State
0x00_0000
0x0
0x0
0x0
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