Samsung S5PC110 Manual page 528

S5PC110_UM
1.4.1.5 Interrupt Enable Register
(VICINTENABLE, R/W, Address=0xF200_0010, 0xF210_0010, 0xF220_0010, 0xF230_0010)
VICINTENABLE
IntEnable [31:0] Enables the interrupt request lines, which allows the interrupts to
1.4.1.6 Interrupt Enable Clear
(VICINTENCLEAR, W, Address=0xF200_0014, 0xF210_0014, 0xF220_0014, 0xF230_0014)
VICINTENCLEAR
IntEnable Clear [31:0]
1.4.1.7 Software Interrupt Register
(VICSOFTINT, R/W, Address=0xF200_0018, 0xF210_0018, 0xF220_0018, 0xF230_0018)
VICSOFTINT
SoftInt [31:0]
Bit
reach the processor.
Read:
0 = Disables Interrupt
1 = Enables Interrupt
Use this register to enable interrupt. The VICINTENCLEAR Register
must be used to disable the interrupt enable.
Write:
0 = No effect
1 = Enables Interrupt.
On reset, all interrupts are disabled.
There is one bit of the register for each interrupt source.
Bit
Clears corresponding bits in the VICINTENABLE Register:
0 = No effect
1 = Disables Interrupt in VICINTENABLE Register.
There is one bit of the register for each interrupt source.
Bit
Setting a bit HIGH generates a software interrupt for the selected
source before interrupt masking.
Read:
0 = Software interrupt inactive
1 = Software interrupt active
Write:
0 = No effect
1 = Enables Software interrupt
There is one bit of the register for each interrupt source.
1 VECTORED INTERRUPT CONTROLLER
Description
Description
Description
Initial State
0x00000000
Initial State
-
Initial State
0x00000000
1-21