Samsung S5PC110 Manual page 970

S5PC110_UM
6.2 KEY FEATURES OF MODEM INTERFACE
•
Asynchronous SRAM interface style interface
•
Supports both Standard mode and Address Muxed mode
•
Supports 16-bit parallel bus for data transfer
•
Supports 16 KB internal dual-port SRAM buffer
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Supports Interrupt request for data exchange
•
Programmable interrupt port address
•
Supports DMA for data transfer without intervention of CPU
6.3 INTERRUPT PORTS
If the Modem chip or AP accesses the interrupt-port (predefined special addresses) interrupts are requested or
cleared. The S5PC110 configures the special address and the default address-map is described in the
Interrupt An Interrupt is requested, when
To AP Modem chip writes at least 1 to
0x1FFF through ADR.
To Modem AP writes 1 to 0xED00_3FFC
through internal-chip AHB bus.
NOTE:
1. There are two address views for MODEMIF, namely, MSM address (ADR) for MODEM chip, and AHB
address for S5PC110. AHB address is twice the size of ADR. For example, 0x3FFC at AHB bus is 0x1FFE at ADR.
helps you to understand it.
This is default value. To change the value use SFR (INT2AP and INT2MSM).
2. Modem interface block has one Interrupt Clear Registers; MSMINTCLR. Modem interface block generates level type
interrupt request and is sustained until the S5PC110 clears the interrupt clear registers by writing any value to the
registers.
Modem chip or S5PC110 reads the data that indicates what event occurred, namely, data transfer requested, data
transfer done, special command issued, etc. − from interrupt port address. That data format should be defined for
communication between the modem chip and S5PC110.
6.3.1 WAKEUP
* S5PC110 MODEM_IF does not support Wakeup Interrupt mode
Table 6-1 Interrupt Request and Clear Conditions
Interrupt is cleared, when
AP writes at least 1 to MSMINTCLR register in
(2)
MODEM IF .
Modem chip writes 1 to the bits at 0x1FFE
through ADR.
6 MODEM INTERFACE
.
Table 6-1
6-2