Samsung S5PC110 Manual page 532

S5PC110_UM
1.4.1.19 VICPCELLID1 Register (VICPCELLID1, R, Address=0xF200_0FF4, 0xF210_0FF4, 0xF220_0FF4,
0xF230_0FF4)
VICPCELLID1
-
VICPCellID1
1.4.1.20 VICPCELLID2 Register (VICPCELLID2, R, Address=0xF200_0FF8, 0xF210_0FF8, 0xF220_0FF8,
0xF230_0FF8)
VICPCELLID2
-
VICPCellID2
1.4.1.21 VICPCELLID3 Register (VICPCELLID3, R, Address=0xF200_0FFC, 0xF210_0FFC, 0xF220_0FFC,
0xF230_0FFC)
VICPCELLID3
-
VICPCellID3
1.4.1.22 FIQ Status Register (TZICFIQStatus, R, Address=0xF280_0000, 0xF290_0000, 0xF2A0_0000,
0xF2B0_0000)
TZICFIQStatus
FIQStatus
1.4.1.23 Raw Interrupt Status Register
(TZICRawIntr, R, Address=0xF280_0004, 0xF290_0004, 0xF2A0_0004, 0xF2B0_0004)
TZICRawIntr
RawIntr
Bit
[31:8] Reserved, read as 0, do not modify.
[7:0] These bits read back as 0xF0.
Bit
[31:8] Reserved, read as 0, do not modify.
[7:0] These bits read back as 0x05.
Bit
[31:8] Reserved, read as 0, do not modify.
[7:0] These bits read back as 0xB1.
Bit
[31:0] Shows the status of the interrupts after masking by the
TZICFIQIntEnable and TZICFIQIntEnClear Registers.
A HIGH bit indicates that the interrupt is active, and
generates an nFIQ interrupt to the processor.
Bit
[31:0] Shows the status of the interrupts before masking by the
TZICFIQIntEnable and TZICFIQIntEnClear Registers.
A HIGH bit indicates that the interrupt is active before
masking.
1 VECTORED INTERRUPT CONTROLLER
Description
Description
Description
Description
Description
Initial State
0x0
0xF0
Initial State
0x0
0x05
Initial State
0x0
0xB1
Initial State
0x00000000
Initial State
-
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