Samsung S5PC110 Manual page 876

S5PC110_UM
4.3.2.6 UTMI Configuration (INSNREG05, R/W, Address = 0xEC20_00A4)
INSNREG05
Reserved
-
-
-
-
-
4.3.2.7 AHB Error Status (INSNREG06, R/W, Address = 0xEC20_00A8)
INSNREG05
Reserved
-
-
-
4.3.2.8 AHB Master Error Address (INSNREG07, R/W, Address = 0xEC20_00AC)
INSNREG05
Bit
[31:18] -
[17] Specifies VBusy (Software RO). The hardware indicates that a
write to this register has occurred and the hardware is
processing the operation defined by the data written. When
the processing is finished, this bit is cleared
[16:13] Specifies VPort (Software R/W).
[12] Specifies VControlLoadM.
1'b0 = Load
•
1'b1 = NOP, (Software R/W)
•
[11:8] Specifies VControl (Software R/W).
[7:0] Specifies VStatus (Software RO).
Bit
[31] AHB Error Captured
Indicator that an AHB error was encountered and values were
captured. To clear this field the application must write a 0 to it.
[30:12] -
[11:9] HBURST value of the control phase at which the AHB error
occurred.
[8:4] Number of beats expected in the burst at which the AHB error
occurred. Valid values are 0 to 6
[3:0] Number of successfully-completed beats in the current burst
before the AHB error occurred.
Bit
[31:0] AHB Master Error Address
AHB address of the control phase at which the AHB error
occurred.
Description
Description
Description
4 USB 2.0 HOST CONTROLLER
Initial State
0x00001000
-
-
-
-
-
Initial State
0x00000000
-
-
-
-
Initial State
0x00000000
4-10