Samsung S5PC110 Manual page 602

S5PC110_UM
SROM_BCn Bit
Tcoh [15:12]
Tcah [11:8]
Tacp [7:4]
Reserved [3:2]
PMC [1:0]
Chip selection hold on nOE
0000 = 0 clock
0001 = 1 clocks
0010 = 2 clocks
0011 = 3 clocks
.............
1100 = 12 clocks
1101 = 13 clocks
1110 = 14 clocks
1111 = 15 clocks
Address holding time after nGCSn
0000 = 0 clock
0001 = 1 clocks
0010 = 2 clocks
0011 = 3 clocks
.............
1100 = 12 clocks
1101 = 13 clocks
1110 = 14 clocks
1111 = 15 clocks
Note: More 1~2 cycles according to bus i/f status
Page mode access cycle @ Page mode
0000 = 0 clock
0001 = 1 clocks
0010 = 2 clocks
0011 = 3 clocks
.............
1100 = 12 clocks
1101 = 13 clocks
1110 = 14 clocks
1111 = 15 clocks
Reserved
Page mode configuration
00 = Normal (1 data)
01 = 4 data
10 = Reserved
11 = Reserved
Description
2 SROM CONTROLLER
Initial State
0000
0000
0000
00
2-10