Samsung S5PC110 Manual page 804

S5PC110_UM
Peripheral BUS
Transmitter
Transmit Buffer Register
Transmit Shifter
Control Buad-rate
Unit Generator
Receiver
Receive Shifter
Receive Buffer Register
In FIFO mode, all bytes of Buffer Register are used as FIFO register.
In non-FIFO mode, only 1 byte of Buffer Register is used as Holding register.
Figure 1-1
1 UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER
Transmit Holding Register
Block Diagram of UART
Transmit FIFO Register
(FIFO mode)
(Non-FIFO mode)
Clock Source
Receive Holding Register
(Non-FIFO mode only)
Receive FIFO Register
(FIFO mode)
TXDn
RXDn
1-2