Samsung S5PC110 Manual page 901

Risc microprocessor
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S5PC110_UM
Register
DOEPINT13
0xEC00_0CA8
DOEPTSIZ13
0xEC00_0CB0
DOEPDMA13
0xEC00_0CB4
DOEPDMAB13
0xEC00_0CBC
DOEPCTL14
0xEC00_0CC0
DOEPINT14
0xEC00_0CC8
DOEPTSIZ14
0xEC00_0CD0
DOEPDMA14
0xEC00_0CD4
DOEPDMAB14
0xEC00_0CDC
DOEPCTL15
0xEC00_0CE0
DOEPINT15
0xEC00_0CE8
DOEPTSIZ15
0xEC00_0CF0
DOEPDMA15
0xEC00_0CF4
DOEPDMAB15
0xEC00_0CFC
NOTE: All HS OTG Controller registers are accessible by word unit with STR/ LDR instructions.
Address
R/W
R/W Specifies the Device OUT Endpoint 13 Interrupt
Register
R/W Specifies the Device OUT Endpoint 13 Transfer
Size Register
R/W Specifies the Device OUT Endpoint 13 DMA
Address Register
R
Specifies the Device OUT Endpoint 13 DMA Buffer
Address Register
R/W Specifies the Device Control OUT Endpoint 14
Control Register
R/W Specifies the Device OUT Endpoint 14 Interrupt
Register
R/W Specifies the Device OUT Endpoint 14 Transfer
Size Register
R/W Specifies the Device OUT Endpoint 14 DMA
Address Register
R
Specifies the Device OUT Endpoint 14 DMA Buffer
Address Register
R/W Specifies the Device Control OUT Endpoint 15
Control Register
R/W Specifies the Device OUT Endpoint 15 Interrupt
Register
R/W Specifies the Device OUT Endpoint 15 Transfer
Size Register
R/W Specifies the Device OUT Endpoint 15 DMA
Address Register
R
Specifies the Device OUT Endpoint 15 DMA Buffer
Address Register
Description
5 USB2.0 HS OTG
Reset Value
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
5-25

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