Dma Engine Overview - Samsung S5PC110 Manual

S5PC110_UM 3 ONENAND CONTROLLER

3.6.4 DMA ENGINE OVERVIEW

To perform data transfer between internal AHB memory (such as OneNAND device) and external AHB memory
(such as SDRAM), the internal dedicated DMA engine is embedded in the OneNAND controller.
The DMA engine supports single transfer, 4-/ 8-/ 16-burst transfer with 8-/ 16-/ 32-bit data width on the AHB. In
addition, it supports even unaligned transfers.
The DMA engine has two AHB master ports. One port can access OneNAND or control registers on the internal
AHB. The other port can access SDRAM on the external AHB (AHB backbone), as shown in 3-9. Each port
Figure
has 32-entry synchronous FIFOs as data buffer, through which two AHB masters of the DMA engine transfer data.
This helps to improve the performance of data transfer, because two AHB master ports of DMA engine access the
source and destination memories at the same time. Note that a general DMA engine has a single AHB master
port, and the memory accesses to the source and destination memories are serialized.
Figure 3-9 Data Transfer between OneNAND and External Memory by the Internal DMA Engine
(OneNAND Read/ Write)
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