Samsung S5PC110 Manual page 442

S5PC110_UM
5.5.2.10 DPM Frequency Register (IECDPMFREQ, R, Address = 0xE080_0024)
IECDPMFREQ
Reserved
DPM Frequency (DPMF)
5.5.2.11 Configuration Fractional Index Map00 Register (IECCFGDCGIDXMAP00, R, Address =
0xE080_0040)
IECCFGDCGIDXMAP00
IECCFGDCGIDXMAP00
5.5.2.12 Configuration Fractional Index Map32 Register (IECCFGDCGIDXMAP32, R, Address =
0xE080_0044)
IECCFGDCGIDXMAP32
IECCFGDCGIDXMAP32
5.5.2.13 Configuration Fractional Index Map32 Register (IECCFGDCGIDXMAP64, R, Address =
0xE080_0048)
IECCFGDCGIDXMAP64
IECCFGDCGIDXMAP64
5.5.2.14 Configuration DVC Index Map Register (IECCFRDVCIDXMAP, R, Address = 0xE080_004C)
IECCFGDVCIDXMAP
-
IECCFGDVCIDXMAP
5.5.2.15 Configuration Performance Map Register0 (IECCFGDCGPERFMAP0, R, Address = 0xE080_0060)
IECCFGDCGPERFMAP0
IECCFGDCGPERFMAP0
5.5.2.16 Configuration Performance Map Register4 (IECCFGDCGPERFMAP4, R, Address = 0xE080_0064)
IECCFGDCGPERFMAP4
IECCFGDCGPERFMAP4
Bit
[31:24] Reserved, read undefined, do not modify.
[23:0] The DPM frequency in kHz.
Bit
[31:0] State of IECCFGDCGIDXMAP [31:0]
Bit
[31:0] State of IECCFGDCGIDXMAP [63:32]
Bit
[31:0] State of IECCFGDCGIDXMAP [95:64]
Bit
[31:24] Reserved, read undefined, do not modify.
[23:0] State of IECCFGDVCIDXMAP [23:0]
Bit
[31:0] State of IECCFGDCGPERFMAP [31:0]
Bit
[31:0] State of IECCFGDCGPERFMAP [63:32]
5 INTELLIGENT ENERGY MANAGEMENT
Description
Description
Description
Description
Description
Description
Description
Initial State
0
From PMU
Initial State
From PMU
Initial State
From PMU
Initial State
From PMU
Initial State
0
From PMU
Initial State
From PMU
Initial State
From PMU
5-25