Samsung S5PC110 Manual page 338

S5PC110_UM
3.7.5.3 Clock Gating Control Register (CLK_GATE_IP1, R/W, Address = 0xE010_0464)
CLK_GATE_IP1
Reserved
CLK_NFCON
Reserved
CLK_SROMC
CLK_CFCON
CLK_NANDXL
Reserved
CLK_USBHOST
CLK_USBOTG
Reserved
CLK_HDMI
CLK_TVENC
CLK_MIXER
CLK_VP
Reserved
CLK_DSIM
Reserved
CLK_FIMD
Bit
[31:29] Reserved
[28] Gating all clocks for NFCON
(0: mask, 1: pass)
[27] Reserved
[26] Gating all clocks for SROM
(0: mask, 1: pass)
[25] Gating all clocks for CFCON
(0: mask, 1:pass)
[24] Gating all clocks for One NAND-XL
(0:mask, 1:pass)
[23:18] Reserved
[17] Gating all clocks for USB HOST
(0: mask, 1: pass)
[16] Gating all clocks for USB OTG
(0: mask, 1: pass)
[15:12] Reserved
[11] Gating all clocks for HDMI link
(0: mask, 1: pass)
[10] Gating all clocks for TVENC
(0: mask, 1: pass)
[9] Gating all clocks for MIXER
(0: mask, 1: pass)
[8] Gating all clocks for VP
(0: mask, 1: pass)
[7:3] Reserved
[2] Gating all clocks for DSIM
(0: mask, 1: pass)
[1] Reserved
[0] Gating all clocks for FIMD
(0: mask, 1: pass)
Description
3 CLOCK CONTROLLER
Gated Clock Name
ACLK_NFCON
ACLK_SROMC
ACLK_CFCON
ACLK_NANDXL
SCLK_NANDXL
ACLK_USBHOST
ACLK_USBOTG
PCLK_HDMI
SCLK_HDMI
ACLK_TVENC
SCLK_TVENC
SCLK_DAC
ACLK_MIXER
SCLK_MIXER
ACLK_VP
PCLK_DSIM
ACLK_FIMD
SCLK_FIMD
Initial State
0x7
1
1
1
1
1
0x3F
1
1
0xF
1
1
1
1
0x1F
1
1
1
3-41