Samsung S5PC110 Manual page 639

S5PC110_UM
3.8.4.2 Interrupt Controller OneNAND Clear Register (INTC_ONENAND_CLR, W, Address = 0xB060_1008)
INTC_ONENAND
_CLR
-
OCINTD
3.8.4.3 Interrupt Controller DMA Mask Register (INTC_DMA_MASK, R/W, Address = 0xB060_1024)
INTC_DMA_MASK
-
DMTD
-
DMTE
-
3.8.4.4 Interrupt Controller OneNAND Mask Register (INTC_ONENAND_MASK, R/W, Address =
0xB060_1028)
INTC_ONENAND_
MASK
-
OMINTD
Bit
[31:2] Reserved
[1:0]
OneNAND Clear INT Done
When this bit is set to 1, the corresponding OSINTD
(OneNAND status INT done) bit flag of the Interrupt Controller
OneNAND Status Register (INTC_ONENAND_STATUS) in the
interrupt controller is cleared to 0. Each bit corresponds to
each OneNAND chip. For example, writing 1 to OCINTD[0] bit
clears OSINTD[0] for OneNAND chip #0.
Bit
[31:25] Reserved
[24]
DMA Mask Transfer Done
When this bit is set to 1, the DSTD (DMA status transfer done)
bit flag of the Interrupt Controller DMA Status Register
(INTC_DMA_STATUS) in the interrupt controller is disabled to
generate an interrupt.
[13:17] Reserved
[16]
DMA Mask Transfer Error
When this bit is set to 1, the DPTE (DMA status transfer error)
bit flag of the Interrupt Controller DMA Status Register
(INTC_DMA_STATUS) in the interrupt controller is disabled to
generate an interrupt.
[15:0] Reserved
Bit
[31:2] Reserved
[1:0]
OneNAND Mask INT Done
When this bit is set to 1, the corresponding OSINTD
(OneNAND status INT done) bit flag of the Interrupt Controller
OneNAND Status Register (INTC_ONENAND_STATUS) in the
interrupt controller is disabled to generate an interrupt. Each bit
corresponds to each OneNAND chip. For example, writing a 1
to OMINTD[0] bit disables OSINTD[0] to generate an interrupt
for OneNAND chip #0.
Description
Description
Description
3 ONENAND CONTROLLER
Initial State
-
00b
Initial State
-
1b
-
1b
-
Initial State
-
11b
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