Samsung S5PC110 Manual page 825

S5PC110_UM
1.6.1.7 Uart FIFO Status Register
•
UFSTAT0, R, Address = 0xE290_0018
•
UFSTAT1, R, Address = 0xE290_0418
•
UFSTAT2, R, Address = 0xE290_0818
UFSTAT3, R, Address = 0xE290_0C18 There are four UART FIFO status registers in the UART block, namely,
UFSTAT0, UFSTAT1, UFSTAT2 and UFSTAT3
UFSTATn
Reserved [31:25] Reserved
Tx FIFO Full
Tx FIFO Count [23:16] Number of data in Tx FIFO
Reserved [15:10] -
Rx FIFO Error
Rx FIFO Full
Rx FIFO Count
Bit
[24] This bit is automatically set to 1 if the transmitted FIFO is full
during transmit operation
0 = Not full
1 = Full
[9] This bit is set to 1 if Rx FIFO contains invalid data which results
from frame error, parity error, or break signal.
[8] This bit is automatically set to 1 if the received FIFO is full during
receive operation
0 = Not full
1 = Full
[7:0] Number of data in Rx FIFO
1 UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER
Description Initial State
0
0
0
0
0
0
0
1-23