Samsung S5PC110 Manual page 915

S5PC110_UM
GINTSTS Bit
PrtInt [24]
ResetDet [23]
FetSusp [22]
incompIP [21]
incompl
SOOUT
Host Port Interrupt
The core sets this bit to indicate a change in port status of one of
the OTG core ports in Host mode. The application must read the
Host Port Control and Status (HPRT) register to determine the
exact event that caused this interrupt. The application must clear
the appropriate status bit in the Host Port Control and Status
register to clear this bit.
Reset Detected Interrupt
The core asserts this interrupt in Device mode when it detects a
reset on the USB in Partial Power-Down mode when the device
is in Suspend. This interrupt is not asserted in Host mode.
Data Fetch Suspended.
This interrupt is valid only in DMA mode. This interrupt indicates
that the core has stopped fetching data for IN endpoints due to
the unavailability of TxFIFO space or Request Queue space. This
interrupt is used by the application for an endpoint mismatch
algorithm
For example, after detecting an endpoint mismatch, the
application:
Sets a global non-periodic IN NAK handshake
•
Disables In endpoints
•
Flushes the FIFO
•
Determines the token sequence from the IN Token Sequence
•
Learning Queue
Re-enables the endpoints
•
Clears the global non-periodic IN NAK handshake
•
If the global non-periodic IN NAK is cleared, the core has not yet
fetched data for the IN endpoint, and the IN token received: the
core generates an "IN token received when FIFO empty"
interrupt. The OTG then sends the host a NAK response. To
avoid this scenario, the application checks the GINSTS. FetSusp
interrupt, which ensures that the FIFO is full before clearing a
global NAK handshake.
Alternatively, the application masks the "IN token received when
FIFO empty" interrupt if clearing a global IN NAK handshake.
Incomplete Periodic Transfer.
In Host mode, the core sets this interrupt bit if there are
incomplete periodic transactions still pending which are
scheduled for the current microframe.
Incomplete Isochronous OUT Transfer.
The Device mode, the core sets this interrupt to indicate that
there is at least one isochronous OUT endpoint on which the
transfer is not complete in the current microframe. This interrupt
is asserted along with the End of Periodic Frame Interrupt
(EOPF) bit in this register.
Description
5 USB2.0 HS OTG
R/W Initial State
R 1'b0
R_W 1'b0
R_SS 1'b0
_WC
R_SS 1'b0
_WC
- -
5-39