Samsung S5PC110 Manual page 640

S5PC110_UM
3.8.4.5 Interrupt Controller DMA Pending Register (INTC_DMA_PEND, R, Address = 0xB060_1044)
INTC_DMA_PEND
-
DPTD
-
DPTE
-
3.8.4.6 Interrupt Controller OneNAND Pending Register (INTC_ONENAND_PEND, R, Address =
0xB060_1048)
INTC_ONENAND_
PEND
-
-
OPINTD
3.8.4.7 Interrupt Controller DMA Status Register (INTC_DMA_STATUS, R, Address = 0xB060_1064)
INTC_DMA_
STATUS
-
DSTD
-
DSTE
-
Bit
[31:25] Reserved
[24]
DMA Pending Transfer Done
This bit is the exact copy of the TD (transfer done) bit flag of
the DMA Status Register (DMA_STATUS)
[13:17] Reserved
[16]
DMA Pending Transfer Error
This bit is the exact copy of the TE (transfer error) bit flag of the
DMA status register (DMA_STATUS)
[15:0] Reserved
Bit
[31:8] Reserved
[7:2] Reserved
[1:0]
OneNAND Pending INT Done
This bits are the exact copy of the INTD (INT done) bit flag of
the OneNAND Interface Status Register
(ONENAND_IF_STATUS)
Bit
[31:25] Reserved
[24]
DMA Status Transfer Done
This bit is logical AND operation result of DPTD (DMA pending
transfer done) bit flag of the interrupt controller DMA pending
register (INTC_DMA_PEND) and inverse of DMTD (DMA mask
transfer done) bit flag of the Interrupt Controller DMA Mask
Register (INTC_DMA_MASK)
[13:17] Reserved
[16]
DMA Status Transfer Error
This bit is logical AND operation result of DPTE (DMA pending
transfer error) bit flag of the interrupt controller DMA pending
register (INTC_DMA_PEND) and inverse of DMTE (DMA mask
transfer error) bit flag of the Interrupt Controller DMA Mask
Register (INTC_DMA_MASK)
[15:0] Reserved
Description
Description
Description
3 ONENAND CONTROLLER
Initial State
-
0b
-
0b
-
Initial State
-
111111b
11b
Initial State
-
0b
-
0b
-
3-38