Samsung S5PC110 Manual page 405

Risc microprocessor
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S5PC110_UM
4.10.4.6 Power Management Register (IDLE_CFG, R/W, Address = 0xE010_C020)
IDLE_CFG
TOP_LOGIC
TOP_MEMORY
ARM_L2CACHE
Reserved
CFG_DIDLE
Bit
[31:30]
Configure TOP logic state
01 = Retention
10 = ON
Other: Reserved
[29:28]
Configure TOP memory state
01 = Retention
10 = ON
Other: Reserved
[27:26]
Configure ARM L2 cache state in DEEP-IDLE mode
00 = OFF
01 = Retention
Other: Reserved
[25:1]
Reserved
[0]
Configure DEEP-IDLE setting for Cortex-A8 core
0 = No DEEP (Cortex-A8 core power on)
1 = DEEP (Cortex-A8 core power off)
Description
4 POWER MANAGEMENT
Initial State
0x1
0x1
0x0
0x000_0000
0
4-45

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