Read Data Capture - Samsung S5PC110 Manual

S5PC110_UM 1 DRAM CONTROLLER

1.2.6 READ DATA CAPTURE

A memory device that receives a read command sends the data to the controller after a read latency (i.e. CAS
latency). After clearing the DQS, the PHY uses the PHY DLL to phase shift the DQS 90 degrees. Using the
shifted DQS, the PHY samples the read data and saves the data into the read data input FIFO, which is located
inside the PHY. Then, the controller fetches the data from the PHY while considering the read latency and the
read fetch delay, and then sends it to the AXI read channel. The following figures show the read data capture
process's timing diagram for each memory type.
Figure 1-6 Timing Diagram of Read Data Capture (DDR2, zero delay, RL=3, rd_fetch=1)
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