Samsung S5PC110 Manual page 660

S5PC110_UM
NFCONT
MECCLock
SECCLock
InitMECC
InitSECC
HW_nCE
Reg_nCE1
Reg_nCE0
MODE
4.5.2.3 Command Register (NFCMMD, R/W, Address = 0xB0E0_0008)
NFCMMD
Reserved [31:8]
REG_CMMD [7:0]
4.5.2.4 Address Register (NFADDR, R/W, Address = 0xB0E0_000C)
NFADDR
Reserved [31:8]
REG_ADDR [7:0]
Bit
[7] Lock Main area ECC generation
0 = Unlock Main area ECC
1 = Lock Main area ECC
Main area ECC status register is
NFMECC0/NFMECC1(0xB0E0_0034/0xB0E0_0038),
[6] Lock Spare area ECC generation.
0 = Unlock Spare ECC
1 = Lock Spare ECC
Spare area ECC status register is NFSECC(0xB0E0_003C),
[5] 1 = Initialize main area ECC decoder/encoder (write-only)
[4] 1 = Initialize spare area ECC decoder/encoder (write-only)
[3] Reserved (HW_nCE)
[2] NAND Flash Memory nRCS[1] signal control
[1] NAND Flash Memory nRCS[0] signal control
0 = Force nRCS[0] to low (Enable chip select)
1 = Force nRCS[0] to High (Disable chip select)
Note: The setting all nCE[3:0] zero can not be allowed. Only
one nCE can be asserted to enable external NAND flash
memory. The lower bit has more priority when user set all
nCE[3:0] zeros.
[0] NAND Flash controller operating mode
0 = Disable NAND Flash Controller
1 = Enable NAND Flash Controller
Bit
Reserved
NAND Flash memory command value
Bit
Reserved
NAND Flash memory address value
Description
Description
Description
4 NAND FLASH CONTROLLER
Initial State
1
1
0
0
0
1
1
0
Initial State
0x000000
0x00
Initial State
0x000000
0x00
4-19