Clocks From Cmu - Samsung S5PC110 Manual

S5PC110_UM
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XXTI and XXTO use wide-range OSC pads.
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XUSBXTI and XUSBXTO use wide range OSC pads.
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XHDMIXTI and XHDMIXTO use wide range OSC pads.
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XRTCXTI and XRTCXTO use OSC pads for RTC.
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ARMCLK specifies clock for Cortex A8 (up to 800 MHz @ 1.1V, 1 GHz @ 1.2V).
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HCLK_MSYS specifies AXI clock for MSYS clock domain, as shown in
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PCLK_MSYS specifies APB clock for MSYS clock domain, as shown in
The maximum operating frequency is up to 100MHz.
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HCLK_DSYS specifies AXI/AHB clock for DSYS clock domain, as shown in
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PCLK_DSYS specifies APB clock for DSYS clock domain, as shown in
The maximum operating frequency is up to 83 MHz.
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HCLK_PSYS specifies AXI/AHB clock for PSYS clock domain, as shown in
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PCLK_PSYS specifies APB clock for PSYS clock domain, as shown in
The maximum operating frequency is up to 66 MHz.
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Special clocks specify all the clocks except bus clock and processor core clock.

3.2.2 CLOCKS FROM CMU

CMU generates internal clocks with intermediate frequencies using clocks from the clock pads (that is, XRTCXTI,
XXTI, XUSBXTI, and XHDMIXTI), four PLLs (that is, APLL, MPLL, EPLL, and VPLL), and USB_OTG PHY clock.
Some of these clocks can be selected, pre-scaled, and provided to the corresponding modules.
It is recommended to use 24MHz input clock source for APLL, MPLL, and EPLL, and 27MHz input clock source
for VPLL.
To generate internal clocks, the following components are used.
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APLL uses SRCLK as input to generate 30MHz ~ 1GHz.
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MPLL uses SRCLK as input to generate 50MHz ~ 2GHz.
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EPLL uses SRCLK as input to generate 10MHz ~ 600MHz.
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VPLL uses SRCLK as input to generate 10MHz ~ 600MHz. This PLL generates 54MHz video clock.
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USB OTG PHY uses XUSBXTI to generate 30MHz and 48MHz.
In typical S5PC110 applications,
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Cortex A8 and MSYS clock domain uses APLL (that is, ARMCLK, HCLK_MSYS, and PCLK_MSYS).
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DSYS and PSYS clock domain (that is, HCLK_DSYS, HCLK_PSYS, PCLK_DSYS, and PCLK_PSYS) and
other peripheral clocks (that is, audio IPs, SPI, and so on) use MPLL and EPLL.
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Video clocks uses VPLL.
Clock controller allows bypassing of PLLs for slow clock. It also connects/ disconnects the clock from each block
(clock gating) using software, resulting in power reduction.
3 CLOCK CONTROLLER
Figure 3-1.
Figure 3-1.
Figure 3-1.
Figure 3-1.
Figure 3-1.
Figure 3-1.
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