Samsung S5PC110 Manual page 634

S5PC110_UM
3.8.3.4 DMA Destination Configuration Register (DMA_DST_CFG, R/W, Address = 0xB060_040C)
DMA_DST_CFG
-
DBL
-
DAM
-
DDW
Bit
[31:19] Reserved
[18:16]
Destination Burst Length
Burst length during the destination memory access on the AHB
for the DMA operation.
This burst length is valid only when the memory address is
aligned. The DMA engine requires that the memory address
should be the multiple of the HSIZE (data width) x HBURST
(burst length) to initiate the burst transfer on the AHB during
the DMA transfer. If this address alignment condition is not
satisfied, the actual burst length on the AHB will be single until
this condition is met.
000b = Single
001b = Reserved
010b = 4-Burst
011b = 8-Burst
100b = 16-Burst
101b = Reserved
110b = Reserved
111b = Reserved
[15:9] Reserved
[8]
Destination Addressing Mode
It specifies Addressing mode during the destination memory
access on the AHB for the DMA operation.
The incremental addressing mode is used for the general DMA
operation and the constant mode is used to access repeatedly
the specific address like a data register.
0b = Incremental addressing mode
1b = Constant addressing mode
[7:2] Reserved
[1:0]
Destination Data Width
Access size during the destination memory access on the AHB
for the DMA operation.
The data width is valid only if the memory address is aligned.
To initiate the AHB transfer, the DMA engine requires that the
memory address should be the multiple of the HSIZE (data
width). If this address alignment condition is not satisfied, the
actual data width on the AHB during the DMA transfer will be
smaller than the access size specified in these bits.
00b = 8-bit (byte)
01b = 16-bit (half word)
10b = 32-bit (word)
11b = Reserved
Description
3 ONENAND CONTROLLER
Initial State
-
100b
-
0b
-
10b
3-32