Samsung S5PC110 Manual page 904

S5PC110_UM
5.8.2.3 USB Reset Control Register (URSTCON, R/W, Address = 0xEC10_0008)
URSTCON Bit
Reserved [31:5]
host_sw_rst [4]
phy_sw_rst1 [3]
phylnk_sw_rst [2]
link_sw_rst [1]
phy_sw_rst0 [0]
Figure 5-4
-
USB Host LINK S/W Reset
USB PHY1, USB Host LINK S/W Reset
The phy1_sw_rst signal must by asserted for at least 10us
OTG Link Core phy_clock domain S/W Reset
OTG Link Core hclk domain S/W Reset
USBPHY0 , LINK 2.0 S/W Reset
The phy_sw_rst0 signal must be asserted for at least 10us
USB PHY Clock Path
Description
5 USB2.0 HS OTG
R/W Initial State
- 29'h0
R/W 1'b0
R/W 1'b1
R/W 1'b0
R/W 1'b0
R/W 1'b1
5-28