Samsung S5PC110 Manual page 566

S5PC110_UM
Register
QOSCONFIG15 0xF000_00DC
DMC1
CONCONTROL 0xF140_0000
MEMCONTROL 0xF140_0004
MEMCONFIG0 0xF140_0008
MEMCONFIG1 0xF140_000C
DIRECTCMD 0xF140_0010
PRECHCONFIG 0xF140_0014
PHYCONTROL0 0xF140_0018
PHYCONTROL1 0xF140_001C
RESERVED 0xF140_0020
PWRDNCONFIG 0xF140_0028
TIMINGAREF 0xF140_0030
TIMINGROW 0xF140_0034
TIMINGDATA 0xF140_0038
TIMINGPOWER 0xF140_003C
PHYSTATUS 0xF140_0040
CHIP0STATUS 0xF140_0048
CHIP1STATUS 0xF140_004C
AREFSTATUS 0xF140_0050
MRSTATUS 0xF140_0054
PHYTEST0 0xF140_0058
PHYTEST1 0xF140_005C
QOSCONTROL0 0xF140_0060
QOSCONFIG0 0xF140_0064
QOSCONTROL1 0xF140_0068
QOSCONFIG1 0xF140_006C
QOSCONTROL2 0xF140_0070
QOSCONFIG2 0xF140_0074
Address R/W
R/W Specifies the Quality of Service Configuration
Register 15
R/W Specifies the Controller Control Register
R/W Specifies the Memory Control Register
R/W Specifies the Memory Chip0 Configuration Register
R/W Specifies the Memory Chip1 Configuration Register
R/W Specifies the Memory Direct Command Register
R/W Specifies the Precharge Policy Configuration
Register
R/W Specifies the PHY Control0 Register
R/W Specifies the PHY Control1 Register
R/W Reserved
R/W Specifies the Dynamic Power Down Configuration
Register
R/W Specifies the AC Timing Register for SDRAM Auto
Refresh
R/W Specifies the AC Timing Register for SDRAM Row
R/W Specifies the AC Timing Register for SDRAM Data
R/W Specifies the AC Timing Register for Power
Specifies the Mode of SDRAM
R Specifies the PHY Status Register
R Specifies the Memory Chip0 Status Register
R Specifies the Memory Chip1 Status Register
R Specifies the Counter Status Register for Auto
Refresh
R Specifies the Memory Mode Registers Status
Register
R/W Specifies the PHY Test Register 0
R Specifies the PHY Test Register 1
R/W Specifies the Quality of Service Control Register 0
R/W Specifies the Quality of Service Configuration
Register 0
R/W Specifies the Quality of Service Control Register 1
R/W Specifies the Quality of Service Configuration
Register 1
R/W Specifies the Quality of Service Control Register 2
R/W Specifies the Quality of Service Configuration
Register 2
Description
1 DRAM CONTROLLER
Reset Value
0x0000_0000
0x0FFF1350
0x00202100
0x40E00312
0x60E00312
0x00000000
0xFF000000
0x00000000
0x00000040
0x00000000
0xFFFF00FF
0x0000040E
0x0F233286
0x12130204
0x0E1B0422
0x0000000X
0x00000000
0x00000000
0x0000FFFF
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
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