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S3F80JB
CLKCON
— System Clock Control Register
Bit Identifier
Reset Value
Read/Write
Addressing Mode
.7 – .5
.4 and .3
.2 – .0
NOTES:
1.
After a reset, the slowest clock (divided by 16) is selected as the system clock. To select faster clock speeds, load the
appropriate values to CLKCON.3 and CLKCON.4.
2.
These selection bits CLKCON.0, .1, .2 are required only for systems that have a main clock and a subsystem clock. The
S3F80JB uses only the main oscillator clock circuit. For this reason, the setting '101B' is invalid.
.7
.6
0
0
R/W
R/W
Register addressing mode only
Not used for S3F80JB
CPU Clock (System Clock) Selection Bits
f
/16
0
0
OSC
f
/8
0
1
OSC
f
/2
1
0
OSC
f
(non-divided)
1
1
OSC
Subsystem Clock Selection Bits
1
0
1
Not used for S3F80JB.
Other value
Select main system clock (MCLK)
.5
.4
.3
0
0
R/W
R/W
R/W
(1)
(2)
CONTROL REGISTERS
D4H Set1 Bank0
.2
.1
0
0
0
R/W
R/W
.0
0
R/W
4-7
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