Samsung S5PC110 Manual page 773

S5PC110_UM
2.8.1.8 Interrupt Control and Status Register (INT_CSTAT, R/W, Address = E260_0020)
INT_CSTAT
Reserved
TWIE
IWIE
TFWIE
TIWIE
ICNTEIE
TCON Write Status
ICNTB Write Status
TFCNTB Write Status
TICNTB Write Status
INTCNT counter expired
Status
Interrupt Enable
Bit
[31:11] Reserved
[10] TCON Write Interrupt Enable
0 = Disable
1 = Enable
[9] ICNTB write Interrupt Enable
0 = Disable
1 = Enable
[8] TFCNTB write Interrupt Enable
0 = Disable
1 = Enable
[7] TICNTB write Interrupt Enable
0 = Disable
1 = Enable
[6] Interrupt counter expired (INTCNT=0) Interrupt Enable.
0 = Disable
1 = Enable
[5] TCON Write Interrupt Status Bit. After user writes value
to TCON, this bit is asserted.
Clear by writing '1' on this bit.
[4] ICNTB Write Interrupt Status Bit. After user writes value
to ICNTB, this bit is asserted.
Clear by writing '1' on this bit.
[3] TFCTNB Write Interrupt Status Bit. After user writes
value to TFCNTB, this bit is asserted.
Clear by writing '1' on this bit.
[2] TICTNB Write Interrupt Status Bit. After user writes value
to TICNTB, this bit is asserted.
Clear by writing '1' on this bit.
[1] Interrupt counter expired (INTCNT=0) Interrupt Status
Bit. When timer interrupt is occurred, this bit is asserted.
Clear by writing '1' on this bit.
[0] Enables Interrupt.
1 = Enable
0 = Disable
Description
2 SYSTEM TIMER
Initial State
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
2-1