Functional Description; Initialization - Samsung S5PC110 Manual

S5PC110_UM

1.2 FUNCTIONAL DESCRIPTION

1.2.1 INITIALIZATION

An Initialization procedure consists of PHY DLL initialization, setting controller register and memory initialization.
For memory initialization, refer to JEDEC specifications and data sheets of memory devices. There are three
different memory types, namely, LPDDR, LPDDR2, and DDR2. According to the memory types, initialization
sequences are as follows.
1.2.1.1 LPDDR
Initialization sequence for LPDDR memory type:
1. To provide stable power for controller and memory device, the controller must assert and hold CKE to a logic
high level. Then apply stable clock. Note: XDDR2SEL should be Low level to hold CKE to high.
2. Set the PhyControl0.ctrl_start_point and PhyControl0.ctrl_inc bit-fields to correct value according to clock
frequency. Set the PhyControl0.ctrl_dll_on bit-field to '1' to activate the PHY DLL.
3. DQS Cleaning: Set the PhyControl1.ctrl_shiftc and PhyControl1.ctrl_offsetc bit-fields to the correct value
according to clock frequency and memory tAC parameters.
4. Set the PhyControl0.ctrl_start bit-field to '1'.
5. Set the ConControl. At this moment, an auto refresh counter should be off.
6. Set the MemControl. At this moment, all power down modes should be off.
7. Set the MemConfig0 register. If there are two external memory chips, also set the MemConfig1 register.
8. Set the PrechConfig and PwrdnConfig registers.
9. Set the TimingAref, TimingRow, TimingData and TimingPower registers according to memory AC
parameters.
10. If QoS scheme is required, set the QosControl0~15 and QosConfig0~15 registers.
11 Wait for the PhyStatus0.ctrl_locked bit-fields to change to '1'. Check whether PHY DLL is locked.
12. PHY DLL compensates the changes of delay amount caused by Process, Voltage and Temperature (PVT)
variation during memory operation. Therefore, it should not be off for reliable operation. PHY DLL can be off if
frequency is low. If off mode is used, set the PhyControl0.ctrl_force bit-field to the correct value according to
the PhyStatus0.ctrl_lock_value[9:2] bit-field for fix delay amount. Clear the PhyControl0.ctrl_dll_on bit-
field to turn off PHY DLL.
13. Confirm whether stable clock issues minimum 200us after power on
14. Issue a PALL command using the DirectCmd register.
15. Issue two Auto Refresh commands using the DirectCmd register.
16. Issue a MRS command using the DirectCmd register to program the operating parameters.
1 DRAM CONTROLLER
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