Samsung S5PC110 Manual page 238

S5PC110_UM
2.2.55.76 GPIO Interrupt Control Registers (GPF0_INT_MASK, R/W, Address = 0xE020_0924)
GPF0_INT_MASK
Reserved
GPF0_INT_MASK[7]
GPF0_INT_MASK[6]
GPF0_INT_MASK[5]
GPF0_INT_MASK[4]
GPF0_INT_MASK[3]
GPF0_INT_MASK[2]
GPF0_INT_MASK[1]
GPF0_INT_MASK[0]
2.2.55.77 GPIO Interrupt Control Registers (GPF1_INT_MASK, R/W, Address = 0xE020_0928)
GPF1_INT_MASK
Reserved
GPF1_INT_MASK[7]
GPF1_INT_MASK[6]
GPF1_INT_MASK[5]
GPF1_INT_MASK[4]
GPF1_INT_MASK[3]
GPF1_INT_MASK[2]
GPF1_INT_MASK[1]
GPF1_INT_MASK[0]
Bit
[31:8] Reserved
[7] 0 = Enables Interrupt
1 = Masked
[6] 0 = Enables Interrupt
1 = Masked
[5] 0 = Enables Interrupt
1 = Masked
[4] 0 = Enables Interrupt
1 = Masked
[3] 0 = Enables Interrupt
1 = Masked
[2] 0 = Enables Interrupt
1 = Masked
[1] 0 = Enables Interrupt
1 = Masked
[0] 0 = Enables Interrupt
1 = Masked
Bit
[31:8] Reserved
[7] 0 = Enables Interrupt
1 = Masked
[6] 0 = Enables Interrupt
1 = Masked
[5] 0 = Enables Interrupt
1 = Masked
[4] 0 = Enables Interrupt
1 = Masked
[3] 0 = Enables Interrupt
1 = Masked
[2] 0 = Enables Interrupt
1 = Masked
[1] 0 = Enables Interrupt
1 = Masked
[0] 0 = Enables Interrupt
1 = Masked
2 GENERAL PURPOSE INPUT/ OUTPUT
Description
Description
Initial State
0
1
1
1
1
1
1
1
1
Initial State
0
1
1
1
1
1
1
1
1
2-203