Pad Mux For Address Configuration - Samsung S5PC110 Manual

S5PC110_UM

1.3.1 PAD MUX FOR ADDRESS CONFIGURATION

PAD Name
Xm1ADDR[0]
Xm1ADDR[1]
Xm1ADDR[2]
Xm1ADDR[3]
Xm1ADDR[4]
Xm1ADDR[5]
Xm1ADDR[6]
Xm1ADDR[7]
Xm1ADDR[8]
Xm1ADDR[9]
Xm1ADDR[10]
Xm1ADDR[11]
Xm1ADDR[12]
Xm1ADDR[13]
Xm1ADDR[14]
Xm1ADDR[15]
Xm1CSn[1]
Xm1CSn[0]
Xm1CKE[1]
Xm1CKE[0]
NOTE:
1. Address Config. 1 : The Number of Banks (MEMCONFIGn.chip_bank) is set under 4banks and the Number of Row
Address Bits(MEMCONFIGn.chip_row) is set under 14bits.
2. Address Config. 2: The Number of Banks (MEMCONFIGn.chip_bank) is set under 4banks and the Number of Row
Address Bits(MEMCONFIGn.chip_row) is set 15 bits.
3. Address Config. 3: The Number of Banks (MEMCONFIGn.chip_bank) is set 8 banks and the Number of Row
Address Bits(MEMCONFIGn.chip_row) is set under 14 bits
4. Address Config. 4: The Number of Banks (MEMCONFIGn.chip_bank) is set 8 banks and the Number of Row
Address Bits(MEMCONFIGn.chip_row) is set 15bits.
5. Address LPDDR2 : The Type of Memory(MEMCONTROL.mem_type) is selected LPDDR2.
Config. 1 Config. 2
ADDR_0 ADDR_0
ADDR_1 ADDR_1
ADDR_2 ADDR_2
ADDR_3 ADDR_3
ADDR_4 ADDR_4
ADDR_5 ADDR_5
ADDR_6 ADDR_6
ADDR_7 ADDR_7
ADDR_8 ADDR_8
ADDR_9 ADDR_9
ADDR_10 ADDR_10
ADDR_11 ADDR_11
ADDR_12 ADDR_12
ADDR_13 ADDR_13
BA_0 BA_0
BA_1 BA_1
CS_1
CS_0 CS_0
CKE_1 ADDR_14
CKE_0 CKE_0
Config. 3 Config. 4
ADDR_0 ADDR_0
ADDR_1 ADDR_1
ADDR_2 ADDR_2
ADDR_3 ADDR_3
ADDR_4 ADDR_4
ADDR_5 ADDR_5
ADDR_6 ADDR_6
ADDR_7 ADDR_7
ADDR_8 ADDR_8
ADDR_9 ADDR_9
ADDR_10 ADDR_10
ADDR_11 ADDR_11
ADDR_12 ADDR_12
ADDR_13 ADDR_13
BA_0 BA_0
BA_1 BA_1
BA_2 BA_2
CS_0 CS_0
ADDR_14
CKE_0 CKE_0
1 DRAM CONTROLLER
LPDDR2
CA_0
CA_1
CA_2
CA_3
CA_4
CA_5
CA_6
CA_7
CA_8
CA_9
CS_1
CS_0
CKE_1
CKE_0
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