Samsung S5PC110 Manual page 818

S5PC110_UM
1.6.1.2 UART Control Register
•
UCON0, R/W, Address = 0xE290_0004
•
UCON1, R/W, Address = 0xE290_0404
•
UCON2, R/W, Address = 0xE290_0804
•
UCON3, R/W, Address = 0xE290_0C04
There are four UART control registers in the UART block, namely, UCON0, UCON1, UCON2 and UCON3.
UCONn
Reserved [31:21]
Tx DMA Burst
Size
Reserved [19:17]
Rx DMA Burst
Size
Reserved [15:11]
Clock Selection
Tx Interrupt Type
Rx Interrupt Type
Rx Time Out
Enable
Rx Error Status
Interrupt Enable
Bit
Reserved
[20] Tx DMA Burst Size
0 = 1 byte (Single)
1 = 4 bytes
Reserved
[16] Rx DMA Burst Size
0 = 1 byte (Single)
1 = 4 bytes
Reserved
[10] Selects PCLK or SCLK_UART (from Clock Controller) clock for
the UART baud rate.
DIV_VAL1) = (PCLK / (bps x 16) ) −1
0 = PCLK:
1 = SCLK_UART:
[9]
Interrupt request type.
0 = Pulse (Interrupt is requested when the Tx buffer is empty in
the Non-FIFO mode or when it reaches Tx FIFO Trigger Level in
the FIFO mode.)
1 = Level (Interrupt is requested when Tx buffer is empty in the
Non-FIFO mode or when it reaches Tx FIFO Trigger Level in the
FIFO mode.)
[8]
Interrupt request type.
0 = Pulse (Interrupt is requested when instant Rx buffer receives
data in the Non-FIFO mode or when it reaches Rx FIFO Trigger
Level in the FIFO mode.)
1 = Level (Interrupt is requested when Rx buffer is receiving data
in the Non-FIFO mode or when it reaches Rx FIFO Trigger Level
in the FIFO mode.)
[7] Enables/ Disables Rx time-out interrupts if UART FIFO is
enabled. The interrupt is a receive interrupt.
0 = Disables
1 = Enables
[6] Enables the UART to generate an interrupt upon an exception,
such as a break, frame error, parity error, or overrun error during
a receive operation.
0 = Does not generate receive error status interrupt.
1 = Generates receive error status interrupt.
1 UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER
Description
DIV_VAL1) = (SCLK_UART / (bps x 16) ) −1
(2)
(2)
Initial State
000
0
000
0
0000
00
0
0
0
0
1-16