Samsung S5PC110 Manual page 914

S5PC110_UM
5.8.3.6 Core Interrupt Register (GINTSTS, R/W, Address = 0xEC00_0014)
This register interrupts the application for system-level events in the current mode of operation (Device mode or
Host mode).
GINTSTS Bit
WkUpInt [31]
SessReqInt [30]
DisconnInt [29]
ConIDSts [28]
Chng
LPM_Int [27]
PTxFEmp [26]
HChInt [25]
Resume/ Remote Wakeup Detected Interrupt
In Device mode, this interrupt is asserted if a resume is detected
on the USB. In Host mode, this interrupt is asserted if a remote
wakeup is detected on the USB.
Session Request/ New Session Detected Interrupt
In Host mode, this interrupt is asserted if a session request is
detected from the device. In Device mode, this interrupt is
asserted if the b_valid signal goes high.
Disconnect Detected Interrupt
Asserted when a device disconnect is detected.
Connector ID Status Change
The core sets this bit if there is a change in connector ID status.
LPM Transaction Received Interrupt
The core asserts this interrupt the device receives an LPM
transaction with a non-ERRORed response. The interrupt is
asserted in Host mode when the device responds to an LPM
token with a non-ERRORed response. or when the host core has
completed LPM transactions for the programmed number of
times (GLPMCFG.RetryCnt). This field is valid only if
OTG_ENABLE_LPM is set to 1 and the Global Core LPM
Configuration register's LPM-Capable (LPMCap) field is set to 1.
Periodic TxFIFO Empty
Asserted if the Periodic Transmit FIFO is either half or completely
empty and there is space for at least one entry to be written in
the Periodic Request Queue. The half or completely empty status
is determined by the Periodic TxFIFO Empty Level bit in the Core
AHB Configuration register.(GAHBCFG.PTFEmpLvl)
Host Channels Interrupt
The core sets this bit to indicate that an interrupt is pending on
one of the channels of the core (in Host mode). The application
must read the Host All Channels Interrupt (HAINT) register to
determine the exact number of the channel on which the interrupt
occurred, and then read the corresponding Host Channel-n
Interrupt (HCINTn) register to determine the exact cause of the
interrupt. The application must clear the appropriate status bit in
the HCINTn register to clear this bit.
Description
5 USB2.0 HS OTG
R/W Initial State
R_SS 1'b0
_WC
R_SS 1'b0
_WC
R_SS 1'b0
_WC
R_SS 1'b0
_WC
R_SS 1'b0
_WC
R 1'b1
R 1'b0
5-38