Samsung S5PC110 Manual page 800

Figure
Number
Figure 1-1 Block Diagram of UART.................................................................................................................... 1-2
Figure 1-2 UART AFC Interface......................................................................................................................... 1-4
Figure 1-3 UART Receives the Five Characters Including Two Errors ............................................................. 1-7
Figure 1-4 IrDA Function Block Diagram ........................................................................................................... 1-8
Figure 1-5 Serial I/O Frame Timing Diagram (Normal UART) ........................................................................... 1-8
Figure 1-6 Infra-Red Transmit Mode Frame Timing Diagram............................................................................ 1-9
Figure 1-7 Infra-Red Receive Mode Frame Timing Diagram............................................................................. 1-9
Figure 1-8 Input Clock Diagram for UART ....................................................................................................... 1-10
Figure 1-9 nCTS and Delta CTS Timing Diagram ........................................................................................... 1-24
Figure 1-10 Block diagram of UINTSP, UINTP and UINTM .............................................................................. 1-30
I 2 C-Bus Block Diagram .................................................................................................................... 2-2
Figure 2-1
Figure 2-2 Start and Stop Condition................................................................................................................... 2-3
I 2 C-Bus Interface Data Format......................................................................................................... 2-4
Figure 2-3
Data Transfer on the I 2 C-Bus........................................................................................................... 2-4
Figure 2-4
Figure 2-5 Acknowledge on the I2C-Bus ........................................................................................................... 2-5
Figure 2-6 Operations for Master/Transmitter Mode.......................................................................................... 2-7
Figure 2-7 Operations for Master/ Receiver Mode............................................................................................. 2-8
Figure 2-8 Operations for Slave/ Transmitter Mode........................................................................................... 2-9
Figure 2-9 Operations for Slave/Receiver Mode.............................................................................................. 2-10
Figure 3-1 SPI Transfer Format ......................................................................................................................... 3-4
Figure 3-2 Auto Chip Select Mode Waveform (CPOL=0, CPHA=0, CH_WIDTH=Byte) ................................. 3-12
Figure 4-1 USB System Block Diagram ............................................................................................................. 4-2
Figure 4-2 USB 2.0 Host Controller Block Diagram........................................................................................... 4-3
Figure 5-1 System Level Block Diagram............................................................................................................ 5-2
Figure 5-2 OTG Link CSR Memory Map............................................................................................................ 5-6
Figure 5-3 OTG FIFO Mapping .......................................................................................................................... 5-7
Figure 5-4 USB PHY Clock Path...................................................................................................................... 5-28
Figure 6-1 Interface with the Modem Chip and the MODEM I/F Block Diagram ............................................... 6-1
Figure 6-2 MODEM I/F Address Mapping.......................................................................................................... 6-3
Figure 6-3 Modem Interface Write Timing Diagram (Standard Mode)............................................................... 6-4
Figure 6-4 Modem Interface Read Timing Diagram (Standard Mode) .............................................................. 6-5
Figure 6-5 Modem Interface Write Timing Diagram (Address Muxed mode) .................................................... 6-6
Figure 6-6 Modem Interface Read Timing Diagram (Address Muxed mode) .................................................... 6-7
Figure 7-1 SDMMC Clock Domain..................................................................................................................... 7-2
Figure 7-2 SD Card Detect Sequence ............................................................................................................... 7-3
Figure 7-3 SD Clock Supply Sequence.............................................................................................................. 7-4
Figure 7-4 SD Clock Stop Sequence ................................................................................................................. 7-5
Figure 7-5 SD Clock Frequency Change Sequence.......................................................................................... 7-6
Figure 7-6 SD Bus Power Control Sequence .................................................................................................... 7-7
Figure 7-7 Change Bus Width Sequence........................................................................................................... 7-8
Figure 7-8 Timeout Setting Sequence ............................................................................................................... 7-9
List of Figures
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